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Previous year question hub

Digital Logic and Data Conversion - Analog and Digital Electronics - Electrical Engineering Previous Year Questions

Practice Digital Logic and Data Conversion - Analog and Digital Electronics - Electrical Engineering previous year questions organised from real papers, with year-wise coverage and clear topic navigation.

25Papers
18Years
74Questions
1Topics

Digital Logic and Data Conversion question pattern

Every graph below is calculated only from this selection.

Questions by year

Year-wise coverage for Digital Logic and Data Conversion. Each bar uses a separate theme-derived color.

Difficulty distribution

How the classified questions are distributed by difficulty.

Medium 44 59.5%
Easy 27 36.5%
Hard 3 4.1%

Question type distribution

MCQ, numerical, multiple-select and other formats found in these papers.

MCQ 66 89.2%
Numerical Answer Type (NAT) 8 10.8%

Subject weightage

Top subjects by unique question coverage.

Electrical Engineering
74 Qs

Most asked topics

Top topics across the included previous year papers.

Analog and Digital Electronics
74 Qs

Subtopic coverage

Top subtopics inside this exact selection.

Digital Logic and Data Conversion
74 Qs

Paper coverage

Question coverage for the most populated papers. Every active PYP paper remains listed below.

Electrical Engineering (EE) 2025
1 Qs
Electrical Engineering (EE) 2024
3 Qs
Electrical Engineering (EE) 2023
3 Qs
Electrical Engineering (EE) 2022
2 Qs
Electrical Engineering (EE) 2021
2 Qs
Electrical Engineering (EE) 2020
3 Qs
Electrical Engineering (EE) 2019
2 Qs
Electrical Engineering (EE) 2018
3 Qs
Electrical Engineering (EE) 2017 [Session 1]
3 Qs
Electrical Engineering (EE) 2017 [Session 2]
2 Qs
Electrical Engineering (EE) 2016 [Session 1]
3 Qs
Electrical Engineering (EE) 2016 [Session 2]
2 Qs
Electrical Engineering (EE) 2014 [Session 2]
4 Qs
Electrical Engineering (EE) 2014 [Session 1]
3 Qs
Electrical Engineering (EE) 2014 [Session 3]
3 Qs
Electrical Engineering (EE) 2013 [Session 1]
3 Qs
Electrical Engineering (EE) 2013 [Session 2]
3 Qs
Electrical Engineering (EE) 2013 [Session 4]
3 Qs
Electrical Engineering (EE) 2013 [Session 3]
2 Qs
Electrical Engineering (EE) 2012
4 Qs
Electrical Engineering (EE) 2011
3 Qs
Electrical Engineering (EE) 2010
4 Qs
Electrical Engineering (EE) 2009
3 Qs
Electrical Engineering (EE) 2008
5 Qs
Electrical Engineering (EE) 2007
5 Qs

Included previous year papers

Newest papers appear first. Sort by year, question coverage or name.

PaperYear / sessionQuestions in this viewOpen
Electrical Engineering (EE) 202520251View paper
Electrical Engineering (EE) 202420243View paper
Electrical Engineering (EE) 202320233View paper
Electrical Engineering (EE) 202220222View paper
Electrical Engineering (EE) 202120212View paper
Electrical Engineering (EE) 202020203View paper
Electrical Engineering (EE) 201920192View paper
Electrical Engineering (EE) 201820183View paper
Electrical Engineering (EE) 2017 [Session 1]20173View paper
Electrical Engineering (EE) 2017 [Session 2]20172View paper
Electrical Engineering (EE) 2016 [Session 1]20163View paper
Electrical Engineering (EE) 2016 [Session 2]20162View paper
Electrical Engineering (EE) 2014 [Session 1]20143View paper
Electrical Engineering (EE) 2014 [Session 2]20144View paper
Electrical Engineering (EE) 2014 [Session 3]20143View paper
Electrical Engineering (EE) 2013 [Session 1]20133View paper
Electrical Engineering (EE) 2013 [Session 2]20133View paper
Electrical Engineering (EE) 2013 [Session 3]20132View paper
Electrical Engineering (EE) 2013 [Session 4]20133View paper
Electrical Engineering (EE) 201220124View paper
Electrical Engineering (EE) 201120113View paper
Electrical Engineering (EE) 201020104View paper
Electrical Engineering (EE) 200920093View paper
Electrical Engineering (EE) 200820085View paper
Electrical Engineering (EE) 200720075View paper

All Digital Logic and Data Conversion previous year questions

Practice every matching question in batches of 20, with every available option.

1
2007 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2007

A, B, C and D are input bits, and Y is the output bit in the XOR gate circuit of the figure below. Which of the following statements about the sum S of A, B, C, D and Y is correct?

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2
2007 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2007

The octal equivalent of the HEX number AB.CD is

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3
2007 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2007

Which one of the following statements regarding the INT (interrupt) and the BRQ (bus request) pins in a CPU is true?

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4
2007 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2007
Suppose Reg contains the 2's complement number 11010110. If this number is divided by 2 the answer should be

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5
2007 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2007

Such a division can be correctly performed by the following set of operations

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6
2008 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2008

An input device is interfaced with Intel 8085A microprocessor as memory mapped I/O. The address of the device is 2500H. In order to input data from the device to accumulator, the sequence of instructions will be

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7
2008 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2008
A 3 line to 8 line decoder, with active low outputs, is used to implement a 3-variable Boolean function as shown in the figure. The simplified form of Boolean function F(A,B,C) implemented in ‘Product of Sum’ form will be
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8
2008 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2008
The truth table of a monoshot shown in the figure is given in the table below: [Table]. Two monoshots, one positive edge triggered and other negative edge triggered, are connected as shown in the figure. The pulse widths of the two monoshot outputs, \( Q_1 \) and \( Q_2 \), are \( T_{ON1} \) and \( T_{ON2} \), respectively. The frequency and the duty cycle of the signal at \( Q_1 \) will respectively be
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9
2008 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2008
The contents (in Hexadecimal) of some of the memory locations in an 8085A based system are given below: [Table]. The contents of stack pointer (SP), program counter (PC) and (H,L) are 2700H, 2100H and 0000H respectively. When the following sequence of instructions are executed, 2100 H: DAD SP ; 2101 H: PCHL ; the contents of (SP) and (PC) at the end of execution will be
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10
2008 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2008
The charge stored in the capacitor at t = 5 μs, will be

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11
2009 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2009

The increasing order of speed of data access for the following devices is (i) Cache Memory (ii) CDROM (iii) Dynamic RAM (iv) Processor Registers (v) Magnetic Tape

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12
2009 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2009

The complete set of only those Logic Gates designated as Universal Gates is

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13
2009 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2009
In an 8085 microprocessor, the contents of the Accumulator, after the following instructions are executed will become
XRA A
MVIB F0H
SUB B
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14
2010 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2010

The TTL circuit shown in the figure is fed with the waveform X (also shown). All gates have equal propagation delay of 10 ns. The output Y of the circuit is

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15
2010 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2010
When a “CALL Addr” instruction is executed, the CPU carries out the following sequential operations internally:
Note: (R) means content of register R
((R)) means content of memory location pointed to by R
PC means Program Counter
SP means Stack Pointer
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16
2010 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2010
The following Karnaugh map represents a function F.
A minimized form of the function F is

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17
2010 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2010
Which of the following circuits is a realization of the above function F ?
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18
2011 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2011

The output Y of the logic circuit given below is

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19
2011 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2011
A portion of the main program to call a subroutine SUB in an 8085 environment is given below.
...
LXI D, DISP
LP: CALL SUB
...
It is desired that control be returned to LP + DISP + 3 when the RET instruction is executed in the subroutine. The set of instructions that precede the RET instruction in the subroutine are
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20
2011 · Electrical Engineering · Analog and Digital Electronics · Digital Logic and Data Conversion
Electrical Engineering (EE) 2011
A two-bit counter circuit is shown below.
If the state \( Q_A Q_B \) of the counter at the clock time \( t_n \) is “10” then the state \( Q_A Q_B \) of the counter at \( t_n+3 \) (after three clock cycles) will be

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Showing 20 of 68 questions