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Pipelining and Hazards - Computer Organization and Architecture - Computer Science & Information Technology Previous Year Questions

Practice Pipelining and Hazards - Computer Organization and Architecture - Computer Science & Information Technology previous year questions organised from real papers, with year-wise coverage and clear topic navigation.

22Papers

16Years

26Questions

1Topics

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26questions

Medium 19 73.1%

Easy 5 19.2%

Hard 2 7.7%

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26questions

Numerical Answer Type (NAT) 14 53.8%

MCQ 11 42.3%

MSQ 1 3.8%

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Computer Science & Information Technology

26 Qs

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Computer Organization and Architecture

26 Qs

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Pipelining and Hazards

26 Qs

Paper coverage

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Computer Science and Information Technology (CS) 2026

2 Qs

Computer Science and Information Technology (CS) 2026

1 Qs

Computer Science & Information Technology (CS) 2025 [Session 2]

1 Qs

Computer Science & Information Technology (CS) 2024 [Session 1]

2 Qs

Computer Science & Information Technology (CS) 2024 [Session 2]

2 Qs

Computer Science & Information Technology (CS) 2023 [Session 2]

1 Qs

Computer Science & Information Technology (CS) 2022 [Session 2]

1 Qs

Computer Science & Information Technology (CS) 2021 [Session 2]

1 Qs

Computer Science & Information Technology (CS) 2020 [Session 2]

1 Qs

Computer Science & Information Technology (CS) 2018 [Session 2]

1 Qs

Computer Science & Information Technology (CS) 2016 [Session 1]

1 Qs

Computer Science & Information Technology (CS) 2016 [Session 2]

1 Qs

Computer Science & Information Technology (CS) 2014 [Session 1]

1 Qs

Computer Science & Information Technology (CS) 2014 [Session 3]

1 Qs

Computer Science & Information Technology (CS) 2013 [Session 1]

1 Qs

Computer Science & Information Technology (CS) 2013 [Session 3]

1 Qs

Computer Science & Information Technology (CS) 2013 [Session 4]

1 Qs

Computer Science & Information Technology (CS) 2011

1 Qs

Computer Science & Information Technology (CS) 2010

1 Qs

Computer Science & Information Technology (CS) 2009

1 Qs

Computer Science & Information Technology (CS) 2008

2 Qs

Computer Science & Information Technology (CS) 2007

1 Qs

Included previous year papers

Newest papers appear first. Search these papers or sort by year and name.

Paper name	Year	PDF
Computer Science and Information Technology (CS) 20262026 2 questions in this view	2026	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science and Information Technology (CS) 20262026 1 questions in this view	2026	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2025 [Session 2]2025 1 questions in this view	2025	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2024 [Session 1]2024 2 questions in this view	2024	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2024 [Session 2]2024 2 questions in this view	2024	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2023 [Session 2]2023 1 questions in this view	2023	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2022 [Session 2]2022 1 questions in this view	2022	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2021 [Session 2]2021 1 questions in this view	2021	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2020 [Session 2]2020 1 questions in this view	2020	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2018 [Session 2]2018 1 questions in this view	2018	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2016 [Session 1]2016 1 questions in this view	2016	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2016 [Session 2]2016 1 questions in this view	2016	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2014 [Session 1]2014 1 questions in this view	2014	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2014 [Session 3]2014 1 questions in this view	2014	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2013 [Session 1]2013 1 questions in this view	2013	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2013 [Session 3]2013 1 questions in this view	2013	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 2013 [Session 4]2013 1 questions in this view	2013	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 20112011 1 questions in this view	2011	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 20102010 1 questions in this view	2010	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 20092009 1 questions in this view	2009	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 20082008 2 questions in this view	2008	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download
Computer Science & Information Technology (CS) 20072007 1 questions in this view	2007	ExamElite PDFs ExamElite solutions Official documents Official question paperOriginal authority-issued PDF Official Download

All Pipelining and Hazards previous year questions

Practice every matching question in batches of 20, with every available option.

2007 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2007

Consider a pipelined processor with the following four stages:
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2 ← R1 + R0
MUL R4, R3, R2 R4 ← R3 * R2
SUB R6, R5, R4 R6 ← R5 – R4

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2008 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2008

Which of the following are NOT true in a pipelined processor? I. Bypassing can handle all RAW hazards. II. Register renaming can eliminate all register carried WAR hazards. III. Control hazard penalties can be eliminated by dynamic branch prediction.

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2008 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2008

The following code is to run on a pipelined processor with one branch delay slot:
I1: ADD R2 ← R7 + R8
I2: SUB R4 ← R5 – R6
I3: ADD R1 ← R2 + R3
I4: STORE Memory[R4] ← R1
BRANCH to Label if R1 == 0
Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?

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2009 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2009

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below :

	S1	S2	S3	S4
I1	2	1	1	1
I2	1	3	2	2
I3	2	1	1	3
I4	1	2	2	2

What is the number of cycles needed to execute the following loop ?
for (i = 1 to 2) {I1; I2; I3; I4;}

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2010 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2010

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?

Instruction	Meaning of instruction
I0: MUL R2, R0, R1	R2 <- R0*R1
I1: DIV R5, R3, R4	R5 <- R3/R4
I2: ADD R2, R5, R2	R2 <- R2+R5
I3: SUB R5, R2, R4	R5 <- R2-R4

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2013 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2013 [Session 1]

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I₁, I₂, I₃, …, I₁₂ is executed in this pipelined processor. Instruction I₁ is the only branch instruction and its branch target is I₉. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

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2013 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2013 [Session 3]

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I₁, I₂, I₃, ..., I₁₂ is executed in this pipelined processor. Instruction I₁ is the only branch instruction and its branch target is I₈. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

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2013 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2013 [Session 4]

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, ..., I12 is executed in this pipelined processor. Instruction I1 is the only branch instruction and its branch target is I2. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

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2014 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2014 [Session 1]

Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is _______________________.

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2014 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2014 [Session 3]

An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is __________.

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2016 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2016 [Session 1]

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is ______________ percent.

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2016 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2016 [Session 2]

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2018 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2018 [Session 2]

The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.
The number of clock cycles required for completion of execution of the sequence of instructions is ______.

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2020 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2020 [Session 2]

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is __________.

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2021 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2021 [Session 2]

Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.
Consider the following sequence of 8 instructions:
ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL
Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The Speedup is defined as follows:
\[ Speedup = \frac{\text{Execution time without operand forwarding}}{\text{Execution time with operand forwarding}} \]
The Speedup achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is __________

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2022 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2022 [Session 2]

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is __________.

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2023 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2023 [Session 2]

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.

The total execution time for executing 100 instructions on this processor is __________ ns.

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2024 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2024 [Session 1]

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

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2024 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2024 [Session 1]

The baseline execution time of a program on a 2 GHz single core machine is 100 nanoseconds (ns). The code corresponding to 90% of the execution time can be fully parallelized. The overhead for using an additional core is 10 ns when running on a multicore system. Assume that all cores in the multicore system run their share of the parallelized code for an equal amount of time.
The number of cores that minimize the execution time of the program is ________

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2024 · Computer Science & Information Technology · Computer Organization and Architecture · Pipelining and Hazards

Computer Science & Information Technology (CS) 2024 [Session 2]

An instruction format has the following structure:
Instruction Number: Opcode destination reg, source reg-1, source reg-2
Consider the following sequence of instructions to be executed in a pipelined processor:
I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8
Which of the following statements is/are TRUE?

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Pipelining and Hazards - Computer Organization and Architecture - Computer Science & Information Technology Previous Year Questions

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Pipelining and Hazards - Computer Organization and Architecture - Computer Science & Information Technology Previous Year Questions

Pipelining and Hazards question pattern

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Paper coverage

Included previous year papers