Computer Organization and Architecture - Computer Science & Information Technology Previous Year Questions
Practice Computer Organization and Architecture - Computer Science & Information Technology previous year questions organised from real papers, with year-wise coverage and clear topic navigation.
28Papers
18Years
145Questions
1Topics
Computer Organization and Architecture question pattern
Every graph below is calculated only from this selection.
Questions by year
Compare question counts across years.
Difficulty distribution
How the classified questions are distributed by difficulty.
145questions
Medium96
66.2%
Easy47
32.4%
Hard2
1.4%
Question type distribution
MCQ, numerical, multiple-select and other formats found in these papers.
145questions
MCQ86
59.3%
Numerical Answer Type (NAT)47
32.4%
MSQ10
6.9%
Fill in the blanks2
1.4%
Subject weightage
Top subjects by unique question coverage.
Computer Science & Information Technology
145 Qs
Most asked topics
Top topics across the included previous year papers.
Computer Organization and Architecture
145 Qs
Subtopic coverage
Top subtopics inside this exact selection.
Memory Hierarchy and I/O
80 Qs
Instruction Sets, ALU and Control Units
39 Qs
Pipelining and Hazards
26 Qs
Paper coverage
Question coverage for the most populated papers. Every active PYP paper remains listed below.
Computer Science and Information Technology (CS) 2026
7 Qs
Computer Science and Information Technology (CS) 2026
6 Qs
Computer Science & Information Technology (CS) 2025 [Session 2]
6 Qs
Computer Science & Information Technology (CS) 2025 [Session 1]
5 Qs
Computer Science & Information Technology (CS) 2024 [Session 1]
6 Qs
Computer Science & Information Technology (CS) 2024 [Session 2]
6 Qs
Computer Science & Information Technology (CS) 2023 [Session 2]
5 Qs
Computer Science & Information Technology (CS) 2022 [Session 2]
5 Qs
Computer Science & Information Technology (CS) 2021 [Session 2]
5 Qs
Computer Science & Information Technology (CS) 2020 [Session 2]
8 Qs
Computer Science & Information Technology (CS) 2019 [Session 2]
4 Qs
Computer Science & Information Technology (CS) 2018 [Session 2]
6 Qs
Computer Science & Information Technology (CS) 2017 [Session 2]
3 Qs
Computer Science & Information Technology (CS) 2017 [Session 1]
2 Qs
Computer Science & Information Technology (CS) 2016 [Session 1]
3 Qs
Computer Science & Information Technology (CS) 2016 [Session 2]
3 Qs
Computer Science & Information Technology (CS) 2014 [Session 1]
4 Qs
Computer Science & Information Technology (CS) 2014 [Session 2]
3 Qs
Computer Science & Information Technology (CS) 2014 [Session 3]
2 Qs
Computer Science & Information Technology (CS) 2013 [Session 1]
7 Qs
Computer Science & Information Technology (CS) 2013 [Session 3]
6 Qs
Computer Science & Information Technology (CS) 2013 [Session 4]
6 Qs
Computer Science & Information Technology (CS) 2013 [Session 2]
1 Qs
Computer Science & Information Technology (CS) 2011
6 Qs
Computer Science & Information Technology (CS) 2010
4 Qs
Computer Science & Information Technology (CS) 2009
6 Qs
Computer Science & Information Technology (CS) 2008
12 Qs
Computer Science & Information Technology (CS) 2007
8 Qs
Browse by subtopics
Open a focused page built from the same verified paper data.
A varied preview from the papers represented in this selection, with every available option.
1
2007 · Computer Science & Information Technology · Computer Organization and Architecture · Memory Hierarchy and I/O
Computer Science & Information Technology (CS) 2007
Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively:
2010 · Computer Science & Information Technology · Computer Organization and Architecture · Memory Hierarchy and I/O
Computer Science & Information Technology (CS) 2010
A main memory unit with a capacity of 4 megabytes is built using 1M × 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
2013 · Computer Science & Information Technology · Computer Organization and Architecture · Memory Hierarchy and I/O
Computer Science & Information Technology (CS) 2013 [Session 1]
In a \(k\)-way set associative cache, the cache is divided into \(v\) sets, each of which consists of \(k\) lines. The lines of a set are placed in sequence one after another. The lines in set \(s\) are sequenced before the lines in set \((s+1)\). The main memory blocks are numbered 0 onwards. The main memory block numbered \(j\) must be mapped to any one of the cache lines from
2013 · Computer Science & Information Technology · Computer Organization and Architecture · Memory Hierarchy and I/O
Computer Science & Information Technology (CS) 2013 [Session 2]
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are sequenced before the lines in set $(s+1)$. The main memory blocks are numbered 0 onwards. The main memory block numbered $j$ must be mapped to any one of the cache lines from