Semiconductor Memories - Digital Circuits - Electronics & Communication Engineering Previous Year Questions

If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in

A \(2 \times 2\) ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to \(D_{ij}\) (where \(i = 0\) or \(1\) and \(j = 0\) or \(1\)) stored in the ROM?