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Previous year question hub

Combinational and Sequential Logic - Digital Logic - Computer Science & Information Technology Previous Year Questions

Practice Combinational and Sequential Logic - Digital Logic - Computer Science & Information Technology previous year questions organised from real papers, with year-wise coverage and clear topic navigation.

23Papers
16Years
36Questions
1Topics

Combinational and Sequential Logic question pattern

Every graph below is calculated only from this selection.

Questions by year

Year-wise coverage for Combinational and Sequential Logic. Each bar uses a separate theme-derived color.

Difficulty distribution

How the classified questions are distributed by difficulty.

Medium 27 75%
Easy 8 22.2%
Hard 1 2.8%

Question type distribution

MCQ, numerical, multiple-select and other formats found in these papers.

MCQ 22 61.1%
Numerical Answer Type (NAT) 10 27.8%
MSQ 4 11.1%

Subject weightage

Top subjects by unique question coverage.

Computer Science & Information Technology
36 Qs

Most asked topics

Top topics across the included previous year papers.

Digital Logic
36 Qs

Subtopic coverage

Top subtopics inside this exact selection.

Combinational and Sequential Logic
36 Qs

Paper coverage

Question coverage for the most populated papers. Every active PYP paper remains listed below.

Computer Science and Information Technology (CS) 2026
1 Qs
Computer Science and Information Technology (CS) 2026
1 Qs
Computer Science & Information Technology (CS) 2025 [Session 2]
2 Qs
Computer Science & Information Technology (CS) 2025 [Session 1]
1 Qs
Computer Science & Information Technology (CS) 2024 [Session 1]
2 Qs
Computer Science & Information Technology (CS) 2024 [Session 2]
1 Qs
Computer Science & Information Technology (CS) 2023 [Session 2]
3 Qs
Computer Science & Information Technology (CS) 2022 [Session 2]
1 Qs
Computer Science & Information Technology (CS) 2021 [Session 2]
2 Qs
Computer Science & Information Technology (CS) 2021 [Session 1]
1 Qs
Computer Science & Information Technology (CS) 2020 [Session 2]
2 Qs
Computer Science & Information Technology (CS) 2019 [Session 2]
2 Qs
Computer Science & Information Technology (CS) 2018 [Session 2]
1 Qs
Computer Science & Information Technology (CS) 2017 [Session 2]
1 Qs
Computer Science & Information Technology (CS) 2016 [Session 1]
2 Qs
Computer Science & Information Technology (CS) 2014 [Session 1]
1 Qs
Computer Science & Information Technology (CS) 2014 [Session 3]
1 Qs
Computer Science & Information Technology (CS) 2013 [Session 1]
1 Qs
Computer Science & Information Technology (CS) 2013 [Session 3]
1 Qs
Computer Science & Information Technology (CS) 2013 [Session 4]
1 Qs
Computer Science & Information Technology (CS) 2010
3 Qs
Computer Science & Information Technology (CS) 2009
1 Qs
Computer Science & Information Technology (CS) 2007
4 Qs

Included previous year papers

Newest papers appear first. Sort by year, question coverage or name.

PaperYear / sessionQuestions in this viewOpen
Computer Science and Information Technology (CS) 202620261View paper
Computer Science and Information Technology (CS) 202620261View paper
Computer Science & Information Technology (CS) 2025 [Session 1]20251View paper
Computer Science & Information Technology (CS) 2025 [Session 2]20252View paper
Computer Science & Information Technology (CS) 2024 [Session 1]20242View paper
Computer Science & Information Technology (CS) 2024 [Session 2]20241View paper
Computer Science & Information Technology (CS) 2023 [Session 2]20233View paper
Computer Science & Information Technology (CS) 2022 [Session 2]20221View paper
Computer Science & Information Technology (CS) 2021 [Session 1]20211View paper
Computer Science & Information Technology (CS) 2021 [Session 2]20212View paper
Computer Science & Information Technology (CS) 2020 [Session 2]20202View paper
Computer Science & Information Technology (CS) 2019 [Session 2]20192View paper
Computer Science & Information Technology (CS) 2018 [Session 2]20181View paper
Computer Science & Information Technology (CS) 2017 [Session 2]20171View paper
Computer Science & Information Technology (CS) 2016 [Session 1]20162View paper
Computer Science & Information Technology (CS) 2014 [Session 1]20141View paper
Computer Science & Information Technology (CS) 2014 [Session 3]20141View paper
Computer Science & Information Technology (CS) 2013 [Session 1]20131View paper
Computer Science & Information Technology (CS) 2013 [Session 3]20131View paper
Computer Science & Information Technology (CS) 2013 [Session 4]20131View paper
Computer Science & Information Technology (CS) 201020103View paper
Computer Science & Information Technology (CS) 200920091View paper
Computer Science & Information Technology (CS) 200720074View paper

All Combinational and Sequential Logic previous year questions

Practice every matching question in batches of 20, with every available option.

1
2007 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2007

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

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2
2007 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2007

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

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3
2007 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2007
In a look-ahead carry generator, the carry generate function Gᵢ and the carry propagate function Pᵢ for inputs Aᵢ and Bᵢ are given by: Pᵢ = Aᵢ ⊕ Bᵢ and Gᵢ = AᵢBᵢ. The expressions for the sum bit Sᵢ and the carry bit Cᵢ₊₁ of the look-ahead carry adder are given by: Sᵢ = Pᵢ ⊕ Cᵢ and Cᵢ₊₁ = Gᵢ + PᵢCᵢ, where C₀ is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pᵢ and Gᵢ are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S₃, S₂, S₁, S₀ and C₄ as its outputs are respectively:
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4
2007 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2007
The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”):
ClearClockLoadCountFunction
1XXXClear to 0
0X00No change
0↑1XLoad input
0↑01Count next
The counter is connected as follows: Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

Question diagram

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5
2009 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2009
Given the following state table of an FSM with two states A and B, one input and one output :
Present State APresent State BInputNext State ANext State BOutput
000001
010100
100010
110100
001010
011001
101001
111000
If the initial state is A = 0, B = 0, what is the minimum length of an input string which will take the machine to the state A = 0, B = 1 with Output = 1 ?
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6
2010 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2010
The Boolean expression for the output \(f\) of the multiplexer shown below is

Question diagram

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7
2010 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2010

What is the boolean expression for the output f of the combinational logic circuit of NOR gates given below?

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8
2010 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2010

In the sequential circuit shown below, if the initial value of the output Q1Q0 is 00, what are the next four values of Q1Q0?

Question diagram

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9
2013 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2013 [Session 1]
In the following truth table, V = 1 if and only if the input is valid.
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10
2013 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2013 [Session 3]
In the following truth table, V = 1 if and only if the input is valid.
InputsOutputs
D0D1D2D3 X0X1V
0000 XX0
1000 001
X100 011
XX10 101
XXX1 111
What function does the truth table represent?
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11
2014 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2014 [Session 1]
Consider the 4-to-1 multiplexer with two select lines S₁ and S₀ given below.
The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is
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12
2014 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2014 [Session 3]
The above synchronous sequential circuit built using JK flip-flops is initialized with \(Q_2Q_1Q_0 = 000\). The state sequence for this circuit for the next 3 clock cycles is
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13
2016 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2016 [Session 1]
Consider the two cascaded 2-to-1 multiplexers as shown in the figure.

The minimal sum of products form of the output X is
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14
2016 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2016 [Session 1]
Consider a carry lookahead adder for adding two \(n\)-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is
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15
2017 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2017 [Session 2]
The next state table of a 2-bit saturating up-counter is given below.
\( Q_1 \)\( Q_0 \)\( Q_1^+ \)\( Q_0^+ \)
0001
0110
1011
1111

The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for \( T_1 \) and \( T_0 \) are
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16
2018 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2018 [Session 2]
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of “in” is _____.

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17
2019 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2019 [Session 2]
Consider three 4-variable functions f1, f2, and f3, which are expressed in sum-of-minterms as f1 = Σ(0, 2, 5, 8, 14), f2 = Σ(2, 3, 6, 8, 14, 15), f3 = Σ(2, 7, 11, 14).
For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:

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18
2019 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2019 [Session 2]
What is the minimum number of 2-input NOR gates required to implement a 4-variable function expressed in sum-of-minterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available. Answer: ______.
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19
2020 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2020 [Session 2]
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is ________.
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20
2020 · Computer Science & Information Technology · Digital Logic · Combinational and Sequential Logic
Computer Science & Information Technology (CS) 2020 [Session 2]
Consider the Boolean function \(z(a, b, c)\).
Which one of the following minterm lists represents the circuit given above?

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