Digital Electronics and Data Conversion - Electronics - Physics Previous Year Questions

1

2007 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2007

Identify the function F generated by the logic network shown

A

\(F = (X + Y) Z\)

B

\(F = Z + Y + \bar{F} X\)

C

\(F = ZY (Y + X)\)

D

\(F = XYZ\)

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2

2007 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2007

In the circuit shown, the ports \(Q_1\) and \(Q_2\) are in the state \(Q_1 = 1, Q_2 = 0\). The circuit is now subjected to two complete clock pulses. The state of these ports now becomes

A

\(Q_2 = 1, Q_1 = 0\)

B

\(Q_2 = 0, Q_1 = 1\)

C

\(Q_2 = 1, Q_1 = 1\)

D

\(Q_2 = 0, Q_1 = 0\)

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3

2007 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2007

The registers \(Q_D, Q_C, Q_B\) and \(Q_A\) shown in the figure are initially in the state 1010 respectively. An input sequence SI = 0101 is applied. After two clock pulses, the state of the shift registers (in the same sequence \(Q_D Q_C Q_B Q_A\)) is

A

1001

B

0100

C

0110

D

1010

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4

2007 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2007

In the circuit shown, the ports Q₁ and Q₂ are in the state Q₁ = 1, Q₂ = 0. The circuit is now subjected to two complete clock pulses. The state of these ports now becomes

A

Q₂ = 1, Q₁ = 0

B

Q₂ = 0, Q₁ = 1

C

Q₂ = 1, Q₁ = 1

D

Q₂ = 0, Q₁ = 0

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5

2007 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2007

The registers Q_D, Q_C, Q_B and Q_A shown in the figure are initially in the state 1010 respectively. An input sequence SI = 0101 is applied. After two clock pulses, the state of the shift registers (in the same sequence Q_D Q_C Q_B Q_A) is

A

1001

B

0100

C

0110

D

1010

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6

2008 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2008

The simplest logic gate circuit corresponding to the Boolean expression, \( Y = P + \overline{P} Q \) is

A

B

C

D

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7

2008 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2008

An analog voltage V is converted into 2-bit binary number. The minimum number of comparators required and their reference voltages are

A

\(3, \left( \frac{V}{4}, \frac{V}{2}, \frac{3V}{4} \right) \)

B

\(3, \left( \frac{V}{3}, \frac{2V}{3}, V \right) \)

C

\(4, \left( \frac{V}{5}, \frac{2V}{5}, \frac{3V}{5}, \frac{4V}{5} \right) \)

D

\(4, \left( \frac{V}{4}, \frac{V}{2}, \frac{3V}{4}, V \right) \)

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8

2008 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2008

The following circuit (where \( R_L >> R \)) performs the operation of

A

OR gate for a negative logic system

B

NAND gate for a negative logic system

C

AND gate for a positive logic system

D

AND gate for a negative logic system

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9

2008 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2008

In the T type master-slave JK flip flop is shown along with the clock and input waveforms. The \( Q_A \) output of flip flop was zero initially. Identify the correct output waveform.

A

Waveform A

B

Waveform B

C

Waveform C

D

Waveform D

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10

2009 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2009

The minimized logic expression for the above map is

A

\(Y = P\overline{R} + \overline{Q}\)

B

\(Y = \overline{Q} \cdot PR\)

C

\(Y = \overline{Q} + PR\)

D

\(Y = Q \cdot \overline{PR}\)

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11

2009 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2009

The corresponding logic implementation using gates is given as:

A

B

C

D

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12

2010 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2010

The voltage resolution of a 12 - bit digital to analog converter (DAC), whose output varies from -10 V to +10 V is, approximately

A

1 mV

B

5 mV

C

20 mV

D

100 mV

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13

2010 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2010

For any set of inputs, A and B, the following circuits give the same output, Q, except one. Which one is it?

A

Circuit A

B

Circuit B

C

Circuit C

D

Circuit D

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14

2011 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2011

The following Boolean expression \(Y = A \cdot \bar{B} \cdot \bar{C} \cdot \bar{D} + A \cdot B \cdot \bar{C} \cdot D + \bar{A} \cdot \bar{B} \cdot \bar{C} \cdot D + \bar{A} \cdot B \cdot C \cdot D + \bar{A} \cdot B \cdot C \cdot \bar{D} + A \cdot B \cdot \bar{C} \cdot \bar{D}\) can be simplified to

A

\(\bar{A} \cdot \bar{B} \cdot C + A \cdot \bar{D}\)

B

\(\bar{A} \cdot B \cdot \bar{C} + A \cdot \bar{D}\)

C

\(A \cdot \bar{B} \cdot \bar{C} + \bar{A} \cdot D\)

D

\(A \cdot B \cdot C + \bar{A} \cdot D\)

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15

2011 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2011

The following Boolean expression
\(Y = A \cdot \overline{B} \cdot \overline{C} \cdot \overline{D} + A \cdot B \cdot \overline{C} \cdot D + \overline{A} \cdot \overline{B} \cdot \overline{C} \cdot D + \overline{A} \cdot \overline{B} \cdot C \cdot D + \overline{A} \cdot B \cdot C \cdot D + A \cdot \overline{B} \cdot \overline{C} \cdot D\)
can be simplified to

A

\(\overline{A} \cdot \overline{B} \cdot C + A \cdot \overline{D}\)

B

\(A \cdot \overline{B} \cdot \overline{C} + A \cdot \overline{D}\)

C

\(A \cdot \overline{B} \cdot \overline{C} + \overline{A} \cdot D\)

D

\(A \cdot B \cdot C + \overline{A} \cdot D\)

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16

2013 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2013

What should be the clock frequency of a 6-bit A/D converter so that its maximum conversion time is 32 \mu s?

A

1 MHz

B

2 MHz

C

0.5 MHz

D

4 MHz

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17

2014 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2014

The minimum number of flip-flops required to construct a mod-75 counter is ______.

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18

2014 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2014

In order to measure a maximum of 4V with a resolution of 1mV using a n-bit A/D converter, working under the principle of ladder network, the minimum value of n is __________.

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19

2016 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2016

For the digital circuit given below, the output X is

A

\(\overline{A} + B \cdot C\)

B

\(\overline{A} \cdot (B + \overline{C})\)

C

\(\overline{A} \cdot (B + C)\)

D

\(A + (B \cdot C)\)

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20

2017 · Physics · Electronics · Digital Electronics and Data Conversion

Physics (PH) 2017

The best resolution that a 7 bit A/D convertor with 5 V full scale can achieve is ______ mV. (up to two decimal places).

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