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Previous year question hub

Logic Circuits and State Machines - Digital Electronics - Instrumentation Engineering Previous Year Questions

Practice Logic Circuits and State Machines - Digital Electronics - Instrumentation Engineering previous year questions organised from real papers, with year-wise coverage and clear topic navigation.

21Papers
18Years
76Questions
1Topics

Logic Circuits and State Machines question pattern

Every graph below is calculated only from this selection.

Questions by year

Year-wise coverage for Logic Circuits and State Machines. Each bar uses a separate theme-derived color.

Difficulty distribution

How the classified questions are distributed by difficulty.

Medium 40 52.6%
Easy 34 44.7%
Hard 2 2.6%

Question type distribution

MCQ, numerical, multiple-select and other formats found in these papers.

MCQ 71 93.4%
Numerical Answer Type (NAT) 3 3.9%
Fill in the blanks 1 1.3%
MSQ 1 1.3%

Subject weightage

Top subjects by unique question coverage.

Instrumentation Engineering
76 Qs

Most asked topics

Top topics across the included previous year papers.

Digital Electronics
76 Qs

Subtopic coverage

Top subtopics inside this exact selection.

Logic Circuits and State Machines
76 Qs

Paper coverage

Question coverage for the most populated papers. Every active PYP paper remains listed below.

Instrumentation Engineering (IN) 2026
2 Qs
Instrumentation Engineering (IN) 2025
4 Qs
Instrumentation Engineering (IN) 2024
2 Qs
Instrumentation Engineering (IN) 2023
6 Qs
Instrumentation Engineering (IN) 2022
4 Qs
Instrumentation Engineering (IN) 2021
3 Qs
Instrumentation Engineering (IN) 2020
3 Qs
Instrumentation Engineering (IN) 2019
4 Qs
Instrumentation Engineering (IN) 2018
5 Qs
Instrumentation Engineering (IN) 2017
2 Qs
Instrumentation Engineering (IN) 2016
6 Qs
Instrumentation Engineering (IN) 2014
1 Qs
Instrumentation Engineering (IN) 2013 [Session 2]
4 Qs
Instrumentation Engineering (IN) 2013 [Session 1]
3 Qs
Instrumentation Engineering (IN) 2013 [Session 3]
3 Qs
Instrumentation Engineering (IN) 2013 [Session 4]
3 Qs
Instrumentation Engineering (IN) 2011
3 Qs
Instrumentation Engineering (IN) 2010
1 Qs
Instrumentation Engineering (IN) 2009
5 Qs
Instrumentation Engineering (IN) 2008
6 Qs
Instrumentation Engineering (IN) 2007
6 Qs

Included previous year papers

Newest papers appear first. Sort by year, question coverage or name.

PaperYear / sessionQuestions in this viewOpen
Instrumentation Engineering (IN) 202620262View paper
Instrumentation Engineering (IN) 202520254View paper
Instrumentation Engineering (IN) 202420242View paper
Instrumentation Engineering (IN) 202320236View paper
Instrumentation Engineering (IN) 202220224View paper
Instrumentation Engineering (IN) 202120213View paper
Instrumentation Engineering (IN) 202020203View paper
Instrumentation Engineering (IN) 201920194View paper
Instrumentation Engineering (IN) 201820185View paper
Instrumentation Engineering (IN) 201720172View paper
Instrumentation Engineering (IN) 201620166View paper
Instrumentation Engineering (IN) 201420141View paper
Instrumentation Engineering (IN) 2013 [Session 1]20133View paper
Instrumentation Engineering (IN) 2013 [Session 2]20134View paper
Instrumentation Engineering (IN) 2013 [Session 3]20133View paper
Instrumentation Engineering (IN) 2013 [Session 4]20133View paper
Instrumentation Engineering (IN) 201120113View paper
Instrumentation Engineering (IN) 201020101View paper
Instrumentation Engineering (IN) 200920095View paper
Instrumentation Engineering (IN) 200820086View paper
Instrumentation Engineering (IN) 200720076View paper

All Logic Circuits and State Machines previous year questions

Practice every matching question in batches of 20, with every available option.

1
2009 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2009

The diodes in the circuit shown are ideal. A voltage of 0 V represents logic 0 and +5 V represents logic 1. The logic function Z realized by the circuit for logic inputs X and Y is

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2
2009 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2009
The minimal sum-of-products expression for the logic function / represented by the given Karnaugh map is
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3
2009 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2009
In the figure shown, the initial state of Q is 0. The output is observed after the application of each clock pulse. The output sequence at Q is
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4
2009 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2009

The binary representation of the decimal number 1.375 is

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5
2009 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2009
The figure above shows a 3-bit ripple counter, with \(Q_2\) as the MSB. The flip-flops are rising-edge triggered. The counting direction is

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6
2010 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2010

The logic gate circuit shown in the adjoining figure realizes the function

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7
2011 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2011
For the Boolean expression \(f = a\bar{b}c + ab\bar{c} + a\bar{b}\bar{c} + ab c + a\bar{b}\bar{c}\), the minimized Product of Sum (PoS) expression is
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8
2011 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2011
The base of the number system for the addition operation \(24 + 14 = 41\) to be true is
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9
2011 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2011
The circuit below shows an up/down counter working with a decoder and a flip-flop. Preset and Clear of the flip-flop are asynchronous active-low inputs. Assuming that the initial value of counter output (Q₂ Q₁ Q₀) as zero, the counter outputs in decimal for 12 clock cycles are
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10
2013 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2013 [Session 1]

A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles

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11
2013 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2013 [Session 1]

The digital circuit shown below uses two negative edge-triggered D-flip-flops. Assuming initial condition of Q1 and Q0 as zero, the output Q1Q0 of this circuit is

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12
2013 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2013 [Session 1]
In the circuit shown below, \(Q_1\) has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If \(V_{CC}\) is +5 V, X and Y are digital signals with 0 V as logic 0 and \(V_{CC}\) as logic 1, then the Boolean expression for Z is
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13
2013 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2013 [Session 2]
In the circuit shown below, $Q_1$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is +5 V, X and Y are digital signals with 0 V as logic 0 and $V_{cc}$ as logic 1, then the Boolean expression for Z is

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14
2013 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2013 [Session 2]

Considering the transformer to be ideal, the transmission parameter 'A' of the 2-port network shown in the figure below is

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15
2013 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2013 [Session 3]
In the circuit shown below, \( Q_1 \) has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If \( V_{cc} \) is +5 V, X and Y are digital signals with 0 V as logic 0 and \( V_{cc} \) as logic 1, then the Boolean expression for Z is
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16
2014 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2014
The figure is a logic circuit with inputs A and B and output Y. \(V_{ss} = + 5\) V. The circuit is of type
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17
2016 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2016
The Boolean expression \(XY + (X' + Y') Z\) is equivalent to
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18
2016 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2016
In the digital circuit given below, F is
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19
2016 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2016
In the circuit given below, the opamp is ideal. The value of current \( I_L \) in microampere is ________.

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20
2016 · Instrumentation Engineering · Digital Electronics · Logic Circuits and State Machines
Instrumentation Engineering (IN) 2016
A 4 to 1 multiplexer to realize a Boolean function \( F (X, Y, Z) \) is shown in the figure below. The inputs Y and Z are connected to the selectors of the MUX (Y is more significant). The canonical sum-of-product expression for \( F (X, Y, Z) \) is

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Showing 20 of 69 questions