Embedded Systems, Data Acquisition and IoT - Digital Electronics - Instrumentation Engineering Previous Year Questions

1

2009 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2009

Consider a system consisting of a microprocessor, memory, and peripheral devices connected by a common bus. During DMA data transfer, the microprocessor

A

only reads from the bus

B

only writes to the bus

C

both reads from and writes to the bus

D

neither reads from nor writes to the bus

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2

2009 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2009

The following is an assembly language program for 8085 microprocessors :

Address	Instruction Code	Mnemonic
1000H	3E 06	MVI A, 06H
1002H	C6 70	ADI 70H
1004H	32 07 10	STA 1007H
1007H	AF	XRA A
1008H	76	HLT

When this program halts, the accumulator contains

A

00H

B

06H

C

70H

D

76H

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3

2010 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2010

The subroutine SBX given below is executed by an 8085 processor. The value in the accumulator immediately after the execution of the subroutine will be:
SBX MVI A,99h
ADI 11h
MOV C,A
RET

A

00h

B

11h

C

99h

D

AAh

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4

2010 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2010

An 8-bit DAC is interfaced with a microprocessor having 16 address lines (\(A_0 \ldots A_{15}\)) as shown in the adjoining figure. A possible valid address for this DAC is

A

3000h

B

4FFFh

C

AFFFh

D

C000h

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5

2010 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2010

In an 8085 processor, the main program calls the subroutine SUB1 given below. When the program returns to the main program after executing SUB1, the value in the accumulator is

Address	Opcode	Mnemonic
2000	3E 00	SUB1: MVI A,00h
2002	CD 05 20	CALL SUB2
2005	3C	SUB2: INR A
2006	C9	RET

A

00

B

01

C

02

D

03

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6

2011 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2011

An 8K×8 bit RAM is interfaced to an 8085 microprocessor. In a fully decoded scheme if the address of the last memory location of this RAM is 4FFFH, the address of the first memory location of the RAM will be

A

1000H

B

2000H

C

3000H

D

4000H

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7

2011 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2011

The number of objects crossing a window sequentially at variable speed is to be counted using interrupt in the 8085 microprocessor. The objects are sensed by an optical source and a detector with associated signal conditioning circuit. The circuit produces a logic high output as long as the an object being in front of the window, and this output is used to interrupt the processor. The duration of the process the interrupt after an interrupt. The best choice of interrupt for an error free counting is

A

RST 5.5

B

RST 6.5

C

RST 7.5

D

INTR

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8

2014 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2014

A microprocessor accepts external interrupts (Ext INT) through a Programmable Interrupt Controller as shown in the figure. Assuming vectored interrupt, a correct sequence of operations when a single external interrupt (Ext INT1) is received will be:

A

Ext INT1 → INTA → Data Read → INT

B

Ext INT1 → INT → INTA → Data Read

C

Ext INT1 → INT → INTA → Address Write

D

Ext INT1 → INT → Data Read → Address Write

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9

2025 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2025

An 8-bit microprocessor has 16-bit address bus (\(A_{15} - A_0\)) where \(A_0\) is the LSB. As shown in Figure (a), it has a pre-installed 4 KB ROM whose starting address is 0000 H. The processor needs to be upgraded by adding a 16 KB RAM as shown in Figure (b). The address range for the newly added RAM is

A

1000 H – 4FFF H

B

3000 H – 6FFF H

C

4000 H – 7FFF H

D

8000 H – BFFF H

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10

2007 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2007

A snapshot of the address, data and control buses of an 8085 microprocessor executing a program is given below:

Address	2020H
Data	24H
IO/M	Logic High
RD	Logic High
WR	Logic Low

The assembly language instruction being executed is

A

IN 24H

B

IN 20H

C

OUT 24H

D

OUT 20H

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11

2007 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2007

8-bit signed integers in 2's complement form are read into the accumulator of an 8085 microprocessor from an I/O port using the following assembly language program segment with symbolic addresses.

BEGIN: IN PORT
RAL
JNC BEGIN
RAR
END: HLT

This program

A

halts upon reading a negative number

B

halts upon reading a positive number

C

halts upon reading a zero

D

never halts

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12

2008 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2008

A 2K×8 bit RAM is interfaced to an 8-bit microprocessor. If the address of the first memory location in the RAM is 0800H, the address of the last memory location will be

A

1000H

B

0FFFH

C

4800H

D

47FFH

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13

2008 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2008

A part of a program written for an 8085 microprocessor is shown below. When the program execution reaches LOOP2, the value of register C will be

A

63H

B

64H

C

99H

D

100H

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14

2008 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2008

If the multiplexer is controlled such that the channels are sequenced every 5 μs as 1, 2, 1, 3, 1, 4, 1, 2, 1, 3, 1, 4, 1, ……, the input connected to channel 1 will be sampled at the rate of

A

25k samples/s

B

50k samples/s

C

100k samples/s

D

200k samples/s

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15

2017 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2017

An 8-bit microcontroller with 16 address lines has 3 fixed interrupts i.e., Int1, Int2 and Int3 with corresponding interrupt vector addresses as 0008H, 0010H and 0018H. To execute a 32-byte long Interrupt Service Subroutine for Int1 starting at the address ISS1, the location 0008H onwards should ideally contain

A

a CALL to ISS1

B

an unconditional JUMP to ISS1

C

a conditional JUMP to ISS1

D

only ISS1

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16

2018 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2018

A portion of an assembly language program written for an 8-bit microprocessor is given below along with explanations. The code is intended to introduce a software time delay. The processor is driven by a 5 MHz clock. The time delay (in \(\mu s\)) introduced by the program is ______.

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17

2019 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2019

In a microprocessor with a 16 bit address bus, the most significant address lines A15 to A12 are used to select a 4096 word memory unit, while lines A0 to A11 are used to address a particular word in the memory unit. If the 3 least significant lines of the address bus A0 to A2 are short-circuited to ground, the addressable number of words in the memory unit is ________.

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18

2021 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2021

A 16-bit microprocessor has twenty address lines (\(A_0\) to \(A_{19}\)) and 16 data lines. The higher eight significant lines of the data bus of the processor are tied to the 8-data lines of a 16 Kbyte memory that can store one byte in each of its 16K address locations. The memory chip should map onto contiguous memory locations and occupy only 16 Kbyte of memory space. Which of the following statement(s) is/are correct with respect to the above design?

A

If the 16 Kbyte of memory chip is mapped with a starting address of 80000H, then the ending address will be 83FFFH.

B

The active high chip-select needed to map the 16 Kbyte memory with a starting address at F0000H is given by the logic expression \((A_{19} \cdot A_{18} \cdot \overline{A_{17}} \cdot A_{16})\).

C

The 16 Kbyte memory cannot be mapped with contiguous address locations with a starting address as 0F0000H using only \(A_{19}\) to \(A_{14}\) for generating chip select.

D

The above chip cannot be interfaced as the width of the data bus of the processor and the memory chip differs.

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19

2026 · Instrumentation Engineering · Digital Electronics · Embedded Systems, Data Acquisition and IoT

Instrumentation Engineering (IN) 2026

A 16-bit processor has 16-bit wide instructions and a few internal registers. Every 16-bit instruction is encoded in a fixed format with one operation code of 7 bits and up to three operands. The operand can be an internal register and each operand is encoded by 3 bits. All the internal registers can be specified in an instruction using three bits.
The correct statement(s) for this processor is/are ____.

A

The processor has 16 internal registers.

B

The processor can support 128 unique operation codes (Opcodes).

C

The processor has up to 8 internal registers.

D

The processor can support 512 unique operation codes (Opcodes).

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