Analog Front Ends and Data Converters - Digital Electronics - Instrumentation Engineering Previous Year Questions

1

2009 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2009

An 8-bit ADC, with 2's complement output, has a nominal input range of \(-2\) V to \(+2\) V. It generates a digital code of 00H for an analog input in the range \(-7.8125\) mV to \(+7.8125\) mV. An input of \(-1.5\) V will produce a digital output of

A

90H

B

96H

C

9BH

D

A0H

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2

2010 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2010

A 4-bit successive approximation type ADC has a full scale value of 15 V. The sequence of the states, the SAR will traverse, for the conversion of an input of 8.15 V is

A

Start conversion -> 1 0 0 0 -> 1 1 0 0 -> 1 0 1 0 -> 1 0 0 1 -> 1 0 0 0 -> End conversion

B

Start conversion -> 1 0 0 0 -> 0 1 0 0 -> 0 0 1 0 -> 0 0 0 1 -> 0 0 0 0 -> End conversion

C

Start conversion -> 1 0 0 0 -> 0 1 0 0 -> 0 1 1 0 -> 0 1 1 1 -> 1 0 0 0 -> End conversion

D

Start conversion -> 1 0 0 0 -> 1 1 0 0 -> 1 1 1 0 -> 1 1 1 1 -> 1 1 1 1 -> End conversion

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3

2011 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2011

Figure below shows a circuit for implementing an 8-bit Digital-to-Analog converter (DAC) using two identical 4-bit DACs with equal reference voltages. Assume that \(b_0\) represents LSB, \(b_7\) MSB and the opamp is ideal. To obtain correct analog values corresponding to an 8-bit DAC at the output \(V_O\), the value of resistor R is

A

\(0.25\ k\Omega\)

B

\(0.5\ k\Omega\)

C

\(1\ k\Omega\)

D

\(8\ k\Omega\)

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4

2011 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2011

A 4-bit successive approximation type of A/D converter has an input range of 0 to 15 volts. The output bit b₁ next to the LSB has a stuck-at-zero fault. The pair of input voltages that produces the same output code word is

A

2 V and 4 V

B

4 V and 6 V

C

1 V and 2 V

D

8 V and 9 V

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5

2014 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2014

An \(N\)-bit ADC has an analog reference voltage \(V\). Assuming zero mean and uniform distribution of the quantization error, the quantization noise power will be:

A

\(\frac{V^2}{12(2^N - 1)^2}\)

B

\(\frac{V^2}{12(2^N - 1)}\)

C

\(\frac{V}{12(2^N - 1)}\)

D

\(\frac{V^2}{\sqrt{12}}\)

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6

2014 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2014

The circuit in the figure represents a counter-based unipolar ADC. When SOC is asserted the counter is reset and clock is enabled so that the counter counts up and the DAC output grows. When the DAC output exceeds the input sample value, the comparator switches from logic 0 to logic 1, disabling the clock and enabling the output buffer by asserting EOC. Assuming all components to be ideal, \(V_{ref}\), DAC output and input to be positive, the maximum error in conversion of the analog sample value is:

A

directly proportional to \(V_{ref}\)

B

inversely proportional to \(V_{ref}\)

C

independent of \(V_{ref}\)

D

directly proportional to clock frequency

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7

2024 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2024

An ADC has a full scale voltage of 1.4 V, resolution of 200 mV, and produces binary output data. The input signal of the ADC has a bandwidth of 500 MHz, and it samples the data at the Nyquist rate. The parallel data output is converted to a serial bit stream using a parallel-to-serial converter. The data rate at the output of the parallel-to-serial converter is ____ Gbps (rounded off to nearest integer).

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8

2008 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2008

The quantization error of the ADC is

A

0 %

B

±0.012 %

C

±0.024 %

D

±0.048 %

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9

2008 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2008

The system is used as a single channel DAS with channel 1 selected as input to the ADC which is set in the continuous conversion mode. For avoiding aliasing error, the cutoff frequency f_c of the filter in channel 1 should be

A

\(f_c < 100 \) kHz

B

\(f_c = 100 \) kHz

C

\(100 \) kHz \(< f_c < 200 \) kHz

D

\(f_c = 200 \) kHz

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10

2018 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2018

The number of comparators required for implementing an 8-bit flash analog-to-digital converter is

A

8

B

128

C

255

D

256

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11

2018 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2018

The sampling rate for Compact Discs (CDs) is 44,000 samples/s. If the samples are quantized to 256 levels and binary coded, the corresponding bit rate (in bits per second) is ______.

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12

2019 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2019

An 8-bit weighted resistor digital-to-analog converter (DAC) has the smallest resistance of 500 \(\Omega\). The largest resistance has a value ______ \(k\Omega\).

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13

2020 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2020

A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is ____

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14

2020 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2020

The address lines A₀ ... A₂ of a 10 bit, 1.023 V full-scale digital to analog converter (DAC) is connected to the data lines D₇ to D₀ of an 8-bit microprocessor, with A₁ and A₀ of the DAC grounded. Now, D₇ ... D₀ is changed from 1010 1010 to 1010 1011. The corresponding change in the output of the DAC (in mV, rounded off to one decimal place) is ____

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15

2020 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2020

The address lines $A_0 \dots A_2$ of a 10 bit, 1.023 V full-scale digital to analog converter (DAC) is connected to the data lines $D_7$ to $D_0$ of an 8-bit microprocessor, with $A_1$ and $A_0$ of the DAC grounded. Now, $D_7 \dots D_0$ is changed from 1010 1010 to 1010 1011. The corresponding change in the output of the DAC (in mV, rounded off to one decimal place) is ____

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16

2021 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2021

For a 4-bit Flash type Analog to Digital Convertor (ADC) with full scale input voltage range “V”, which of the following statement(s) is/are true?

A

The ADC requires 15 comparators.

B

The ADC requires one 4 to 2 priority encoder and 4 comparators.

C

A change in the input voltage by \(\frac{V}{16}\) will always flip MSB of the output.

D

A change in the input voltage by \(\frac{V}{16}\) will always flip the LSB of the output.

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17

2021 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2021

A 10-bit ADC has a full-scale of 10.230 V, when the digital output is (11 1111 1111)₂. The quantization error of the ADC in millivolt is _____.

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18

2022 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2022

An analog-to-digital converter with resolution 0.01 V converts analog signals between 0 V to +10 V to an unsigned binary output. The minimum number of bits (in integer) in the output is ______

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19

2022 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2022

A resistor ladder digital-to-analog converter (DAC) receives a digital input that results in the circuit having the state as shown in the figure. For this digital input, the Thevenin voltage, Vth, and Thevenin resistance, Rth, as seen at the output node are ________

A

Vth = 0.5 V, Rth = 1 kΩ

B

Vth = 0.5 V, Rth = 2 kΩ

C

Vth = 1 V, Rth = 1 kΩ

D

Vth = 1 V, Rth = 2 kΩ

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20

2026 · Instrumentation Engineering · Digital Electronics · Analog Front Ends and Data Converters

Instrumentation Engineering (IN) 2026

The maximum signal to quantization noise ratio (SQNR) for a 16-bit analog-to-digital converter is approximately ______ dB.

A

48

B

68

C

88

D

98

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