Difficulty distribution
How the classified questions are distributed by difficulty.
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Practice Deductive and Inductive Reasoning - Logic - General Aptitude (GA) previous year questions organised from real papers, with year-wise coverage and clear topic navigation.
Every graph below is calculated only from this selection.
Year-wise coverage for Deductive and Inductive Reasoning. Each bar uses a separate theme-derived color.
How the classified questions are distributed by difficulty.
MCQ, numerical, multiple-select and other formats found in these papers.
Top subjects by unique question coverage.
Top topics across the included previous year papers.
Top subtopics inside this exact selection.
Question coverage for the most populated papers. Every active PYP paper remains listed below.
Newest papers appear first. Sort by year, question coverage or name.
| Paper | Year / session | Questions in this view | Open |
|---|---|---|---|
| Instrumentation Engineering (IN) 2026 | 2026 | 2 | View paper |
| Instrumentation Engineering (IN) 2025 | 2025 | 2 | View paper |
| Instrumentation Engineering (IN) 2024 | 2024 | 1 | View paper |
| Instrumentation Engineering (IN) 2023 | 2023 | 2 | View paper |
| Instrumentation Engineering (IN) 2022 | 2022 | 2 | View paper |
| Instrumentation Engineering (IN) 2021 | 2021 | 1 | View paper |
| Instrumentation Engineering (IN) 2019 | 2019 | 1 | View paper |
| Instrumentation Engineering (IN) 2015 | 2015 | 6 | View paper |
| Instrumentation Engineering (IN) 2014 | 2014 | 1 | View paper |
| Instrumentation Engineering (IN) 2012 | 2012 | 4 | View paper |
Practice every matching question in batches of 20, with every available option.
There are eight bags of rice looking alike, seven of which have equal weight and one is slightly heavier. The weighing balance is of unlimited capacity. Using this balance, the minimum number of weighings required to identify the heavier bag is

Consider the logic circuit with input signal TEST shown in the figure. All gates in the figure shown have identical non-zero delay. The signal TEST which was at logic LOW is switched to logic HIGH and maintained at logic HIGH. The output

In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and Y are


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