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Previous year question hub

Sequential Circuits - Digital Circuits - Electronics & Communication Engineering Previous Year Questions

Practice Sequential Circuits - Digital Circuits - Electronics & Communication Engineering previous year questions organised from real papers, with year-wise coverage and clear topic navigation.

23Papers
18Years
40Questions
1Topics

Sequential Circuits question pattern

Every graph below is calculated only from this selection.

Questions by year

Compare question counts across years.

Difficulty distribution

How the classified questions are distributed by difficulty.

Medium 36 90%
Easy 3 7.5%
Hard 1 2.5%

Question type distribution

MCQ, numerical, multiple-select and other formats found in these papers.

MCQ 27 67.5%
Numerical Answer Type (NAT) 10 25%
Fill in the blanks 3 7.5%

Subject weightage

Top subjects by unique question coverage.

Electronics & Communication Engineering
40 Qs

Most asked topics

Top topics across the included previous year papers.

Digital Circuits
40 Qs

Subtopic coverage

Top subtopics inside this exact selection.

Sequential Circuits
40 Qs

Paper coverage

Question coverage for the most populated papers. Every active PYP paper remains listed below.

Electronics and Communication Engineering (EC) 2026
3 Qs
Electronics & Communication Engineering (EC) 2025
2 Qs
Electronics & Communication Engineering (EC) 2024
1 Qs
Electronics & Communication Engineering (EC) 2023
2 Qs
Electronics & Communication Engineering (EC) 2022
1 Qs
Electronics & Communication Engineering (EC) 2021
1 Qs
Electronics & Communication Engineering (EC) 2020
2 Qs
Electronics & Communication Engineering (EC) 2019
2 Qs
Electronics & Communication Engineering (EC) 2018
2 Qs
Electronics & Communication Engineering (EC) 2017 [Session 1]
4 Qs
Electronics & Communication Engineering (EC) 2017
1 Qs
Electronics & Communication Engineering (EC) 2017 [Session 2]
1 Qs
Electronics & Communication Engineering (EC) 2016 [Session 2]
2 Qs
Electronics & Communication Engineering (EC) 2016 [Session 3]
1 Qs
Electronics & Communication Engineering (EC) 2014 [Session 1]
1 Qs
Electronics & Communication Engineering (EC) 2014 [Session 2]
1 Qs
Electronics & Communication Engineering (EC) 2014 [Session 3]
1 Qs
Electronics & Communication Engineering (EC) 2012
2 Qs
Electronics & Communication Engineering (EC) 2011
3 Qs
Electronics & Communication Engineering (EC) 2010
1 Qs
Electronics & Communication Engineering (EC) 2009
2 Qs
Electronics & Communication Engineering (EC) 2008
2 Qs
Electronics & Communication Engineering (EC) 2007
2 Qs

Included previous year papers

Newest papers appear first. Search these papers or sort by year and name.

Paper nameYearPDFAttempt
Electronics and Communication Engineering (EC) 20262026
3 questions in this view		2026
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Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20252025
2 questions in this view		2025
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ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20242024
1 questions in this view		2024
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ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20232023
2 questions in this view		2023
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Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20222022
1 questions in this view		2022
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Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20212021
1 questions in this view		2021
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Official question paperOriginal authority-issued PDF Official Download Official answer keyOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20202020
2 questions in this view		2020
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Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20192019
2 questions in this view		2019
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Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20182018
2 questions in this view		2018
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Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20172017
1 questions in this view		2017
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Electronics & Communication Engineering (EC) 2017 [Session 1]2017
4 questions in this view		2017
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ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 2017 [Session 2]2017
1 questions in this view		2017
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ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 2016 [Session 2]2016
2 questions in this view		2016
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ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 2016 [Session 3]2016
1 questions in this view		2016
ExamElite PDFs
ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 2014 [Session 1]2014
1 questions in this view		2014
ExamElite PDFs
ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 2014 [Session 2]2014
1 questions in this view		2014
ExamElite PDFs
ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 2014 [Session 3]2014
1 questions in this view		2014
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Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20122012
2 questions in this view		2012
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Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20112011
3 questions in this view		2011
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Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20102010
1 questions in this view		2010
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ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20092009
2 questions in this view		2009
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Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20082008
2 questions in this view		2008
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Official documents
Official question paperOriginal authority-issued PDF Official Download
Electronics & Communication Engineering (EC) 20072007
2 questions in this view		2007
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ExamElite solutions
Official documents
Official question paperOriginal authority-issued PDF Official Download

All Sequential Circuits previous year questions

Practice every matching question in batches of 20, with every available option.

1
2007 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2007
The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: \(X = 0, Y = 1;\) \(X = 0, Y = 0;\) \(X = 1, Y = 1.\) The corresponding stable P, Q outputs will be
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2
2007 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2007
For the circuit shown, the counter state (\(Q_1 Q_0\)) follows the sequence
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3
2008 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2008
For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is ΔT.
Which of the following waveforms correctly represents the output at Q1?

Question diagram

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4
2008 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2008

For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible.

Which of the following statements is true?

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5
2009 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2009
Refer to the NAND and NOR latches shown in the figure. The inputs \((P_1, P_2)\) for both the latches are first made \((0,1)\) and then, after a few seconds, made \((1,1)\). The corresponding stable outputs \((Q_1, Q_2)\) are

Question diagram

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6
2009 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2009
What are the counting states \((Q_1, Q_2)\) for the counter shown in the figure below ?

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7
2010 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2010

Assuming that all flip-flops are in reset condition initially, the count sequence observed at Qa in the circuit shown is

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8
2011 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2011

When the output Y in the circuit below is “1”, it implies that data has

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9
2011 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2011
The output of a 3-stage Johnson (twisted-ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all states of the counter to be unset initially. The waveform which represents the D/A converter output $V_o$ is

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10
2011 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2011
Two D flip-flops are connected as a synchronous counter that goes through the following $Q_B Q_A$ sequence $00 \to 11 \to 01 \to 10 \to 00 \to \dots$
The connections to the inputs $D_A$ and $D_B$ are
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11
2012 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2012
Consider the given circuit. In this circuit, the race around

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12
2012 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2012

The state transition diagram for the logic circuit shown is

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13
2014 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2014 [Session 1]
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?
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14
2014 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2014 [Session 2]
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is

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15
2014 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2014 [Session 3]
The circuit shown in the figure is a

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16
2016 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2016 [Session 2]
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor \(R = 10\) k\(\Omega\) and the supply voltage is 5 V. The D flip-flops \(D_1\), \(D_2\), \(D_3\), \(D_4\) and \(D_5\) are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor \(R\) is _____

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17
2016 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2016 [Session 2]
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure. Which one of the following statements is correct?
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18
2016 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2016 [Session 3]
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
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19
2017 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2017

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0. If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is ________

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20
2018 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits
Electronics & Communication Engineering (EC) 2018
A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is ______.
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