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Previous year question hub

Combinational Logic and Boolean Minimization - Digital Circuits - Electronics & Communication Engineering Previous Year Questions

Practice Combinational Logic and Boolean Minimization - Digital Circuits - Electronics & Communication Engineering previous year questions organised from real papers, with year-wise coverage and clear topic navigation.

28Papers
18Years
85Questions
1Topics

Combinational Logic and Boolean Minimization question pattern

Every graph below is calculated only from this selection.

Questions by year

Compare question counts across years.

Difficulty distribution

How the classified questions are distributed by difficulty.

Medium 54 63.5%
Easy 28 32.9%
Hard 3 3.5%

Question type distribution

MCQ, numerical, multiple-select and other formats found in these papers.

MCQ 69 81.2%
MSQ 8 9.4%
Numerical Answer Type (NAT) 7 8.2%
Fill in the blanks 1 1.2%

Subject weightage

Top subjects by unique question coverage.

Electronics & Communication Engineering
85 Qs

Most asked topics

Top topics across the included previous year papers.

Digital Circuits
85 Qs

Subtopic coverage

Top subtopics inside this exact selection.

Combinational Logic and Boolean Minimization
85 Qs

Paper coverage

Question coverage for the most populated papers. Every active PYP paper remains listed below.

Electronics and Communication Engineering (EC) 2026
3 Qs
Electronics & Communication Engineering (EC) 2025
2 Qs
Electronics & Communication Engineering (EC) 2024
4 Qs
Electronics & Communication Engineering (EC) 2023
2 Qs
Electronics & Communication Engineering (EC) 2022
4 Qs
Electronics & Communication Engineering (EC) 2021
2 Qs
Electronics & Communication Engineering (EC) 2019
5 Qs
Electronics & Communication Engineering (EC) 2018
5 Qs
Electronics & Communication Engineering (EC) 2017
4 Qs
Electronics & Communication Engineering (EC) 2017 [Session 2]
4 Qs
Electronics & Communication Engineering (EC) 2017 [Session 1]
1 Qs
Electronics & Communication Engineering (EC) 2016 [Session 3]
4 Qs
Electronics & Communication Engineering (EC) 2016 [Session 1]
3 Qs
Electronics & Communication Engineering (EC) 2016 [Session 2]
3 Qs
Electronics & Communication Engineering (EC) 2014 [Session 1]
4 Qs
Electronics & Communication Engineering (EC) 2014 [Session 4]
4 Qs
Electronics & Communication Engineering (EC) 2014 [Session 2]
2 Qs
Electronics & Communication Engineering (EC) 2014 [Session 3]
2 Qs
Electronics & Communication Engineering (EC) 2013 [Session 2]
2 Qs
Electronics & Communication Engineering (EC) 2013 [Session 3]
2 Qs
Electronics & Communication Engineering (EC) 2013 [Session 4]
2 Qs
Electronics & Communication Engineering (EC) 2013 [Session 1]
1 Qs
Electronics & Communication Engineering (EC) 2012
3 Qs
Electronics & Communication Engineering (EC) 2011
2 Qs
Electronics & Communication Engineering (EC) 2010
3 Qs
Electronics & Communication Engineering (EC) 2009
5 Qs
Electronics & Communication Engineering (EC) 2008
3 Qs
Electronics & Communication Engineering (EC) 2007
4 Qs

Included previous year papers

Newest papers appear first. Search these papers or sort by year and name.

Paper nameYearPDFAttempt
Electronics and Communication Engineering (EC) 20262026
3 questions in this view
2026
Electronics & Communication Engineering (EC) 20252025
2 questions in this view
2025
Electronics & Communication Engineering (EC) 20242024
4 questions in this view
2024
Electronics & Communication Engineering (EC) 20232023
2 questions in this view
2023
Electronics & Communication Engineering (EC) 20222022
4 questions in this view
2022
Electronics & Communication Engineering (EC) 20212021
2 questions in this view
2021
Electronics & Communication Engineering (EC) 20192019
5 questions in this view
2019
Electronics & Communication Engineering (EC) 20182018
5 questions in this view
2018
Electronics & Communication Engineering (EC) 20172017
4 questions in this view
2017
Electronics & Communication Engineering (EC) 2017 [Session 1]2017
1 questions in this view
2017
Electronics & Communication Engineering (EC) 2017 [Session 2]2017
4 questions in this view
2017
Electronics & Communication Engineering (EC) 2016 [Session 1]2016
3 questions in this view
2016
Electronics & Communication Engineering (EC) 2016 [Session 2]2016
3 questions in this view
2016
Electronics & Communication Engineering (EC) 2016 [Session 3]2016
4 questions in this view
2016
Electronics & Communication Engineering (EC) 2014 [Session 1]2014
4 questions in this view
2014
Electronics & Communication Engineering (EC) 2014 [Session 2]2014
2 questions in this view
2014
Electronics & Communication Engineering (EC) 2014 [Session 3]2014
2 questions in this view
2014
Electronics & Communication Engineering (EC) 2014 [Session 4]2014
4 questions in this view
2014
Electronics & Communication Engineering (EC) 2013 [Session 1]2013
1 questions in this view
2013
Electronics & Communication Engineering (EC) 2013 [Session 2]2013
2 questions in this view
2013
Electronics & Communication Engineering (EC) 2013 [Session 3]2013
2 questions in this view
2013
Electronics & Communication Engineering (EC) 2013 [Session 4]2013
2 questions in this view
2013
Electronics & Communication Engineering (EC) 20122012
3 questions in this view
2012
Electronics & Communication Engineering (EC) 20112011
2 questions in this view
2011
Electronics & Communication Engineering (EC) 20102010
3 questions in this view
2010
Electronics & Communication Engineering (EC) 20092009
5 questions in this view
2009
Electronics & Communication Engineering (EC) 20082008
3 questions in this view
2008
Electronics & Communication Engineering (EC) 20072007
4 questions in this view
2007

All Combinational Logic and Boolean Minimization previous year questions

Practice every matching question in batches of 20, with every available option.

1
2007 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2007
The Boolean function \(Y = AB + CD\) is to be realized using only 2-input NAND gates. The minimum number of gates required is
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2
2007 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2007
The Boolean expression \(Y = \overline{A} \overline{B} \overline{C} D + \overline{A} B \overline{C} D + A \overline{B} \overline{C} D + A B \overline{C} D\) can be minimized to
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3
2007 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2007
The circuit diagram of a standard TTL NOT gate is shown in the figure. When \(V_i = 2.5\text{ V}\), the modes of operation of the transistors will be
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4
2007 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2007

In the following circuit, \(X\) is given by

Question diagram

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5
2008 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2008

The logic function implemented by the following circuit at the terminal OUT is

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6
2008 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2008
Which of the following Boolean Expressions correctly represents the relation between P, Q, R and M1?

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7
2008 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2008
For the circuit shown in the following figure, I0-I3 are inputs to the 4 : 1 multiplexer. R (MSB) and S are control bits.
The output Z can be represented by

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8
2009 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2009

The full forms of the abbreviations TTL and CMOS in reference to logic families are

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9
2009 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2009
If \(X = 1\) in the logic equation \(\left[X + Z\left\{\overline{Y} + \left(\overline{Z} + X\overline{Y}\right)\right\}\right]\left[\overline{X} + \overline{Z}\left(X + Y\right)\right] = 1\), then
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10
2009 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2009
What are the minimum number of 2-to-1 multiplexers required to generate a 2-input AND gate and a 2-input Ex-OR gate ?
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11
2009 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2009
If segments a to g are considered as functions of P1 and P2, then which of the following is correct ?

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12
2009 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2009
What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the driver for this 7-segment display ?
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13
2010 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2010

For the output F to be 1 in the logic circuit shown, the input combination should be

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14
2010 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2010

In the circuit shown, the device connected to Y5 can have address in the range

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15
2010 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2010

The Boolean function realized by the logic circuit shown is

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16
2011 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2011

The logic function implemented by the circuit below is (ground implies a logic “0”)

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17
2011 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2011

The output Y in the circuit below is always “1” when

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18
2012 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2012

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

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19
2012 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2012

In the circuit shown

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20
2012 · Electronics & Communication Engineering · Digital Circuits · Combinational Logic and Boolean Minimization
Electronics & Communication Engineering (EC) 2012
In the sum of products function \( f(X, Y, Z) = \sum(2, 3, 4, 5) \), the prime implicants are
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Showing 20 of 81 questions