Sequential Circuits - Digital Circuits - Electronics & Communication Engineering Previous Year Questions

1

2012 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2012

Consider the given circuit. In this circuit, the race around

A

does not occur

B

occurs when CLK = 0

C

occurs when CLK = 1 and A = B = 1

D

occurs when CLK = 1 and A = B = 0

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2

2012 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2012

The state transition diagram for the logic circuit shown is

A

B

C

D

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3

2014 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2014 [Session 1]

The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

A

Input A is connected to $\bar{Q}2$

B

Input A is connected to $Q2$

C

Input A is connected to $\bar{Q}1$ and S is complemented

D

Input A is connected to $\bar{Q}1$

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4

2014 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2014 [Session 2]

The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is

A

01110....

B

01010....

C

00110....

D

01100....

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5

2014 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2014 [Session 3]

The circuit shown in the figure is a

A

Toggle Flip Flop

B

JK Flip Flop

C

SR Latch

D

Master-Slave D Flip Flop

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6

2016 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2016 [Session 2]

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor \(R = 10\) k\(\Omega\) and the supply voltage is 5 V. The D flip-flops \(D_1\), \(D_2\), \(D_3\), \(D_4\) and \(D_5\) are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor \(R\) is _____

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7

2016 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2016 [Session 2]

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure. Which one of the following statements is correct?

A

Transitions from State A are ambiguously defined.

B

Transitions from State B are ambiguously defined.

C

Transitions from State C are ambiguously defined.

D

All of the state transitions are defined unambiguously.

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8

2016 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2016 [Session 3]

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

A

mod-5 counter

B

mod-6 counter

C

mod-7 counter

D

mod-8 counter

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9

2017 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2017

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0. If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is ________

A

X is the mother-in-law of R

B

P and R are not married to each other

C

P is a son of X and Y

D

Q cannot be married to R

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10

2018 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2018

A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is ______.

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11

2018 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2018

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data D_in using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of ΔT/T_CK = 0.15, where the parameters ΔT and T_CK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.
If the probability of input data bit (D_in) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is ______.

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12

2019 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2019

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz. The frequency of the signal at \( Q_2 \) is ______ kHz.

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13

2019 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2019

The state transition diagram for the circuit shown is

A

State diagram with Q=0 and Q=1, transitions labeled with A=0 and A=1

B

State diagram with Q=0 and Q=1, transitions labeled with A=0 and A=1

C

State diagram with Q=0 and Q=1, transitions labeled with A=0 and A=1

D

State diagram with Q=0 and Q=1, transitions labeled with A=0 and A=1

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14

2020 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2020

The state diagram of a sequence detector is shown below. State S0 is the initial state of the sequence detector. If the output is 1, then

A

the sequence 01010 is detected.

B

the sequence 01011 is detected.

C

the sequence 01110 is detected.

D

the sequence 01001 is detected.

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15

2020 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2020

For the components in the sequential circuit shown below, \( t_{pd} \) is the propagation delay, \( t_{setup} \) is the setup time, and \( t_{hold} \) is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _____ MHz.

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16

2021 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2021

The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is 500 MHz.
Starting from the initial value of the flip-flop outputs \(Q_2Q_1Q_0 = 1 1 1\) with \(D_2 = 1\), the minimum number of triggering clock edges after which the flip-flop outputs \(Q_2Q_1Q_0\) becomes 1 0 0 (in integer) is __________.

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17

2022 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2022

For the circuit shown, the clock frequency is \(f_0\) and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ________.

A

frequency is \(f_0/4\) and duty cycle is 50%

B

frequency is \(f_0/4\) and duty cycle is 25%

C

frequency is \(f_0/2\) and duty cycle is 50%

D

frequency is \(f_0\) and duty cycle is 25%

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18

2023 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2023

The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are

A

1000, 3

B

333.33, 1

C

2000, 3

D

333.33, 3

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19

2023 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2023

In a given sequential circuit, initial states are \(Q_1 = 1\) and \(Q_2 = 0\). For a clock frequency of 1 MHz, the frequency of signal \(Q_2\) in kHz, is ______ (rounded off to the nearest integer).

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20

2024 · Electronics & Communication Engineering · Digital Circuits · Sequential Circuits

Electronics & Communication Engineering (EC) 2024

The sequence of states \( (Q_1 Q_0) \) of the given synchronous sequential circuit is ______.

A

00 → 10 → 11 → 00

B

11 → 00 → 10 → 01 → 00

C

01 → 10 → 11 → 00 → 01

D

00 → 01 → 10 → 00

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