Numerical Computation and Estimation - Numerical Computation and Estimation - General Aptitude (GA) Previous Year Questions

Consider the following functions from positive integers to real numbers: \( 10, \sqrt{n}, n, \log_2 n, \frac{100}{n} \). The CORRECT arrangement of the above functions in increasing order of asymptotic complexity is:

The \( n \)-bit fixed-point representation of an unsigned real number \( X \) uses \( f \) bits for the fraction part. Let \( i = n - f \). The range of decimal values for \( X \) in this representation is

Consider a database that has the relation schema EMP (EmpId, EmpName, and DeptName). An instance of the schema EMP and a SQL query on it are given below.

EMP
EmpId	EmpName	DeptName
1	XYA	AA
2	XYB	AA
3	XYC	AA
4	XYD	AA
5	XYE	AB
6	XYF	AB
7	XYG	AB
8	XYH	AC
9	XYI	AC
10	XYJ	AC
11	XYK	AD
12	XYL	AD
13	XYM	AE

SELECT AVG(EC.Num) FROM EC WHERE (DeptName, Num) IN     (SELECT DeptName, COUNT(EmpId) AS         EC(DeptName, Num)      FROM EMP      GROUP BY DeptName)

The output of executing the SQL query is ______.

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is __________.

A computer network uses polynomials over GF(2) for error checking with 8 bits as information bits and uses x^3 + x + 1 as the generator polynomial to generate the check bits. In this network, the message 01011011 is transmitted as

Let A be an array of 31 numbers consisting of a sequence of 0's followed by a sequence of 1's. The problem is to find the smallest index i such that A[i] is 1 by probing the minimum number of locations in A. The worst case number of probes performed by an optimal algorithm is __________.

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence

Instr. No.	Instruction
i	add R2, R3, R4
i+1	sub R5, R6, R7
i+2	cmp R1, R9, R10
i+3	beq R1, Offset

If the target of the branch instruction is i, then the decimal value of the Offset is __________.

Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:
(i) a naive pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is __________.

Find the smallest number y such that y × 162 is a perfect cube.