Instruction Sets, ALU and Control Units - Computer Organization and Architecture - Computer Science & Information Technology Previous Year Questions

1

2007 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2007

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is

A

10

B

11

C

20

D

21

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2

2007 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2007

Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is

A

100

B

101

C

102

D

110

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3

2007 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2007

Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction "INC R3", what return address will be pushed on to the stack?

A

1005

B

1020

C

1024

D

1040

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4

2008 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2008

Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code.
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation.
III. The amount of increment depends on the size of the data item accessed.

A

I only

B

II only

C

III only

D

II and III only

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5

2008 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2008

Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor?
I. It must be a trap instruction.
II. It must be a privileged instruction.
III. An exception cannot be allowed to occur during execution of an RFE instruction.

A

I only

B

II only

C

I and II only

D

I, II and III only

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6

2008 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2008

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
I. function locals and parameters
II. register saves and restores
III. instruction fetches

A

I only

B

II only

C

III only

D

I, II and III

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7

2008 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2008

For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false,

A

the instruction following the conditional branch instruction in memory is executed

B

the first instruction in the fall through path is executed

C

the first instruction in the taken path is executed

D

the branch takes longer to execute than any other instruction

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8

2009 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2009

A CPU generally handles an interrupt by executing an interrupt service routine

A

As soon as an interrupt is raised.

B

By checking the interrupt register at the end of fetch cycle.

C

By checking the interrupt register after finishing the execution of the current instruction.

D

By checking the interrupt register at fixed time intervals.

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9

2013 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2013 [Session 1]

Consider the following sequence of micro-operations.
MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR
Which one of the following is a possible operation performed by this sequence?

A

Instruction fetch

B

Operand fetch

C

Conditional branch

D

Initiation of interrupt service

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10

2014 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2014 [Session 1]

Consider two processors P₁ and P₂ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P₂ takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P₁. If the clock frequency of P₁ is 1GHz, then the clock frequency of P₂ (in GHz) is _________.

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11

2016 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2016 [Session 2]

Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

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12

2018 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2018 [Session 2]

Consider the following processor design characteristics.
I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit
Which of the characteristics above are used in the design of a RISC processor?

A

I and II only

B

II and III only

C

I and III only

D

I, II and III

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13

2018 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2018 [Session 2]

The following are some events that occur after a device controller issues an interrupt while process \(L\) is under execution.
(P) The processor pushes the process status of \(L\) onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of \(L\) from the control stack.
(T) The processor loads the new PC value based on the interrupt.
Which one of the following is the correct order in which the events above occur?

A

QPTRS

B

PTRSQ

C

TRPQS

D

QTPRS

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14

2018 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2018 [Session 2]

A processor has 16 integer registers (R0, R1, . . . , R15) and 64 floating point registers (F0, F1, . . . , F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).
The maximum value of N is ______.

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15

2020 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2020 [Session 2]

Consider the following statements.
I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.
Which of the above statements is/are TRUE?

A

I and II only

B

I and IV only

C

I and III only

D

III only

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16

2020 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2020 [Session 2]

Consider the following data path diagram.
Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.
1. R2r, TEMP1r, ALUadd, TEMP2w
2. R1r, TEMP1w
3. PCr, MARw, MEMr
4. TEMP2r, R0w
5. MDRr, IRw
Which one of the following is the correct order of execution of the above steps?

A

2, 1, 4, 5, 3

B

1, 2, 4, 3, 5

C

3, 5, 2, 1, 4

D

3, 5, 1, 2, 4

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17

2020 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2020 [Session 2]

Consider three registers R1, R2, and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.
If \(R3 = \frac{R1}{R2}\), what is the value stored in R3?

A

0x40800000

B

0xC0800000

C

0x83400000

D

0xC8500000

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18

2020 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2020 [Session 2]

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is __________.

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19

2021 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2021 [Session 2]

Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is __________ bits per second.

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20

2021 · Computer Science & Information Technology · Computer Organization and Architecture · Instruction Sets, ALU and Control Units

Computer Science & Information Technology (CS) 2021 [Session 2]

If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer?

A

0x6665

B

0x0001

C

0x4243

D

0x0100

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