Digital Logic and Data Converters - Analog and Digital Electronics - Biomedical Engineering Previous Year Questions

1

2021 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2021

In the circuit shown below, Y is a 2-bit (Y₁Y₀) output of the combinational logic. What is the maximum value of Y for any given digital inputs, A₁A₀ and B₁B₀?

A

01

B

10

C

00

D

11

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2

2021 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2021

In the block diagram shown below, an analog signal, \(V_{IN} = \sin(2\pi 10^6 t)\) is quantized by a 10-bit Nyquist ADC. Later, 4 LSBs are dropped and 6 MSBs are converted to an analog signal (\(V_{OUT}\)) while using a 6-bit DAC. Assume uniform distribution for the quantization noise. The peak SQNR at the output of DAC is ____ dB.

A

61.96

B

25.84

C

49.92

D

37.88

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3

2022 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2022

In the circuit diagram shown below, the logic gates operate with a supply voltage of 1 V. NAND and XNOR have 200 ps and 400 ps input-to-output delay, respectively.
At time t = T, A(t) = 0, B(t) = 1 and Z(t) = 0. When the inputs are changed to A(t) = 1, B(t) = 0 at t = 2T, a 1 V pulse is observed at Z. The pulse width of the 1 V pulse is ______ ps.

A

100

B

200

C

400

D

600

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4

2022 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2022

Input bits X and Y are added by using the combinational logic as shown below. S represents the sum of the two bits. For a correct implementation of the sum, the signals D₀, D₁, D₂, D₃ are __________, respectively.

A

1, 0, 0, 1

B

0, 1, 0, 1

C

1, 0, 1, 1

D

0, 1, 1, 0

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5

2023 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2023

An 8 bit successive approximation Analog to Digital Converter (ADC) has a clock frequency of 1 MHz. Assume that the start conversion and end conversion signals occupy one clock cycle each. Among the following options, what is the maximum frequency that this ADC can sample without aliasing?

A

0.9 kHz

B

9.9 kHz

C

49.9 kHz

D

99.9 kHz

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6

2023 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2023

\( Q, R, S \) are Boolean variables and \( \oplus \) is the XOR operator. Select the CORRECT option(s).

A

\((Q \oplus R) \oplus S = Q \oplus (R \oplus S) \)

B

\((Q \oplus R) \oplus S = 0 \) when any two of the Boolean variables \((Q, R, S) \) are 0 and the third variable is 1

C

\((Q \oplus R) \oplus S = 1 \) when \(Q = R = S = 1 \)

D

\(( (Q \oplus R) \oplus (R \oplus S) ) \oplus (Q \oplus S) = 1 \)

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7

2024 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2024

The circuit shown in the figure functions as which one of the following digital circuit blocks?

A

Negative level triggered D-latch

B

Positive level triggered D-latch

C

Negative edge triggered D-flip-flop

D

Positive edge triggered D-flip-flop

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8

2025 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2025

For an 8-bit Digital to Analog Converter (DAC), the binary input 0000 0000 results in 0 V, and 1111 1111 results in 5 V. The output of the DAC for an input of 1011 0111 is __________ (in volts, rounded off to two decimal places).

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9

2026 · Biomedical Engineering · Analog and Digital Electronics · Digital Logic and Data Converters

Biomedical Engineering (BM) 2026

In the following digital circuit, the delay of both the NAND gates is 4 nanoseconds (ns) and the delay of the NOT gate is 1 ns. If a 10 MHz clock signal with 50% duty cycle is provided as the input, the duty cycle of the output is __________ %
(Answer in integer)

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